1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a layout in which wire distances between a data input/output unit and a plurality of internal circuits are nonuniform.
2. Description of Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) employs external terminals including a data input/output terminal, an address terminal, a command terminal, and the like. Among these external terminals, the data input/output terminal provides high-speed data transfer with a plurality of banks, and thus it is desired that wire distances between a data input/output unit connected to the data input/output terminal and each of the banks are uniform.
However, as shown in FIG. 7A, distances between each of banks 1 to 4 and a data input/output unit 5 are nonuniform in some layouts. In such cases, data transfer times vary among the banks due to the differences in distances between far and near ends (see Japanese Patent Application Laid-open No. H8-139287). When the data transfer times vary among the banks, a period during which data is available is reduced. This necessitates elimination of the differences in data transfer times resulting from the differences in distances between far and near ends.
FIGS. 7B and 7C are schematic diagrams of configurations of a conventional semiconductor memory device in which the differences in data transfer times are eliminated.
In the semiconductor memory device shown in FIG. 7B, by making a detour of a bus line, wire lengths between each of the banks 1 to 4 and the data input/output unit 5 are uniformized. More specifically, data read from the banks 1 and 2 are supplied via a buffer 11 to a bus line 21 and further supplied via a buffer 13 to a bus line 23. On the other hand, data read from the banks 3 and 4 are supplied via a buffer 12 to a bus line 22 and further supplied via the buffer 13 to the bus line 23. As shown in FIG. 7B, the bus line 23 is connected to the data input/output unit 5 and commonly provided to each of the banks 1 to 4. Thereby, the wire distances between each of the banks 1 to 4 and the data input/output unit 5 are made uniform, and thus the differences in data transfer times resulting from the differences between far and near ends are eliminated.
However, in the semiconductor memory device shown in FIG. 7B, the bus line is merely detoured, and thus there is a problem in that a wire density is increased. Specifically, because there are the bus lines 22 and 23 side by side in an area near the data input/output unit 5, the wire density in this area is doubled. For example, when the number of input/output bits is 16 and a burst length is four bits, data transfer using the bus lines 21 to 23 is performed in units of 64 (=16×4) bits, and thus each of the bus lines 21 to 23 is configured by 64 wires. In this case, it is necessary to form 128 wires in the area near the data input/output unit 5, and accordingly, there arises a problem that the wire density in this area significantly increases.
In the semiconductor memory device shown in FIG. 7C, wire loads in the banks 1 to 4 are made uniform by short-circuiting a bus line. Thereby, the differences in data transfer times resulting from the differences between far and near ends are eliminated. More specifically, the buffers 11 and 12 are short-circuited by using a same bus line 24, and thereby, the wire loads in the banks 1 to 4 are made uniform.
However, in the semiconductor memory device shown in FIG. 7C, the wire loads of the bus line 24 become very large, which adversely increases the data transfer times. To solve this problem, it is necessary to lower a resistance by increasing a wire width of the bus line 24. In this case, however, not only an area occupied by the bus line 24 is increased but also a parasitic capacitance of the bus line 24 is increased. Therefore, power consumption increases.
As described above, although it is possible to eliminate the differences in data transfer times, the conventional semiconductor memory devices have the problems such as significant increase in the wire density and increase in the power consumption. The problems can occur not only in the semiconductor memory device but also in all the semiconductor devices having layouts in which wire distances between a data input/output unit and a plurality of internal circuits are nonuniform.